The present invention relates, in general, to semiconductor structures and, more particularly, to a silicon on insulator semiconductor structure having both complementary bipolar and CMOS devices.
A fundamental requirement of integrated circuit manufacture is providing electrical isolation between different devices which comprise an integrated circuit. Electrical isolation is particularly important when monolithically integrating bipolar junction transistors with MOS transistors. It has long been recognized that superior isolation may be achieved by using a high quality insulating material such as silicon dioxide rather than by techniques such as p-n junction isolation. More particularly, isolation techniques employing some form of thin film silicon on insulator (SOI) offer the additional advantages of reduced capacitive coupling, elimination of CMOS latch-up, and simpler fabrication techniques.
The prior art includes numerous methods for fabricating bipolar transistors in bulk silicon which utilize a vertically oriented structure. While vertical structures are suitable to bulk silicon, they are difficult to fabricate in a very thin film. In addition, such structures do not take full advantage of the low parasitic potential of thin film SOI. A method for fabricating a horizontal bipolar transistor on an SOI substrate was described in the paper "A Thin-Base Lateral Bipolar Transistor Fabricated on Bonded SOI", by N. Higaki et al., 1991 VLSI symposium technical digest, pages 53 to 54, which is incorporated herein by reference. This method allows for fabrication of bipolar transistors on an SOI substrate, however the method of fabrication produces a long thin base area with electrical contact provided only at either end of the base structure. The resultant high base resistance degrades the device performance, reducing achievable bandwidth, noise, and switching speed. Another method for fabricating a horizontal bipolar transistor on an SOI substrate was presented in the paper "A NOVEL HIGH-PERFORMANCE LATERAL BIPOLAR ON SOI" by G. G. Shahidi et al., 1991 IEDM, pp 26-1.1-26-1.4. This method addresse the base resistance problem, but requires added process complexity to form a polycrystalline silicon spacer on only one side of the base opening.
Accordingly, it would be advantageous to have a method for fabricating both complementary bipolar and CMOS (BiCMOS) devices using a thin film SOI method which allows a much simplified lateral isolation between devices. The method should utilize horizontal device structures so as to minimize parasitic effects, especially base resistance. Ideally, the method should use the minimum number of mask steps, fabricate self-aligned transistors and should integrate fabrication of both complementary bipolar and CMOS devices into a single manufacturing flow requiring a minimum of extra steps devoted solely to one device type.